add skippable
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parent
206c82b9e4
commit
d97cb74f3f
2 changed files with 27 additions and 1 deletions
5
main.go
5
main.go
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@ -3,6 +3,7 @@
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package main
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package main
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import (
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import (
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"errors"
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"flag"
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"flag"
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"fmt"
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"fmt"
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"log"
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"log"
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@ -108,6 +109,10 @@ func readRegs(client modbus.Client, start, qty uint16) {
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}
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}
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val, err := reg.read(data[(addr-start-1)*2:])
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val, err := reg.read(data[(addr-start-1)*2:])
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if err != nil {
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if err != nil {
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if errors.Is(err, errSkippableRead) {
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log.Printf("Couldn't parse input register data, skipping: %v", err)
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continue
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}
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log.Fatalf("Couldn't parse input register data: %v", err)
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log.Fatalf("Couldn't parse input register data: %v", err)
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}
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}
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//fmt.Printf("%s: %v %s\n", reg.name, val, reg.unit)
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//fmt.Printf("%s: %v %s\n", reg.name, val, reg.unit)
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@ -1,5 +1,11 @@
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package main
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package main
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import (
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"encoding/binary"
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"errors"
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"fmt"
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)
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type register struct {
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type register struct {
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name string
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name string
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conv func([]byte) (float64, error)
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conv func([]byte) (float64, error)
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@ -40,5 +46,20 @@ var sungrowInputRegs = map[uint16]*register{
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5113: {"daily_running_time", u16, 1, "m"},
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5113: {"daily_running_time", u16, 1, "m"},
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5144: {"total_power_yield_2", u32, 0.1, "kWh"},
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5144: {"total_power_yield_2", u32, 0.1, "kWh"},
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5148: {"frequency_2", u16, 0.01, "Hz"},
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5148: {"frequency_2", frequency2, 0.01, "Hz"},
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}
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var errSkippableRead = errors.New("skip read")
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func frequency2(data []byte) (float64, error) {
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n := binary.BigEndian.Uint16(data)
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if n == 0xFFFF {
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// probably a misread
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return 0, fmt.Errorf("likely misread: frequency_2 read %v", n)
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}
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if n == 100 {
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// this translates as 1 Hz, which is unlikely
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return 0, fmt.Errorf(" %w: frequency_2 is 1.00Hz", errSkippableRead)
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}
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return float64(n), nil
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}
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}
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