add skippable

This commit is contained in:
Josh Deprez 2021-01-12 10:45:52 +11:00
parent 206c82b9e4
commit d97cb74f3f
2 changed files with 27 additions and 1 deletions

View file

@ -3,6 +3,7 @@
package main package main
import ( import (
"errors"
"flag" "flag"
"fmt" "fmt"
"log" "log"
@ -108,6 +109,10 @@ func readRegs(client modbus.Client, start, qty uint16) {
} }
val, err := reg.read(data[(addr-start-1)*2:]) val, err := reg.read(data[(addr-start-1)*2:])
if err != nil { if err != nil {
if errors.Is(err, errSkippableRead) {
log.Printf("Couldn't parse input register data, skipping: %v", err)
continue
}
log.Fatalf("Couldn't parse input register data: %v", err) log.Fatalf("Couldn't parse input register data: %v", err)
} }
//fmt.Printf("%s: %v %s\n", reg.name, val, reg.unit) //fmt.Printf("%s: %v %s\n", reg.name, val, reg.unit)

View file

@ -1,5 +1,11 @@
package main package main
import (
"encoding/binary"
"errors"
"fmt"
)
type register struct { type register struct {
name string name string
conv func([]byte) (float64, error) conv func([]byte) (float64, error)
@ -40,5 +46,20 @@ var sungrowInputRegs = map[uint16]*register{
5113: {"daily_running_time", u16, 1, "m"}, 5113: {"daily_running_time", u16, 1, "m"},
5144: {"total_power_yield_2", u32, 0.1, "kWh"}, 5144: {"total_power_yield_2", u32, 0.1, "kWh"},
5148: {"frequency_2", u16, 0.01, "Hz"}, 5148: {"frequency_2", frequency2, 0.01, "Hz"},
}
var errSkippableRead = errors.New("skip read")
func frequency2(data []byte) (float64, error) {
n := binary.BigEndian.Uint16(data)
if n == 0xFFFF {
// probably a misread
return 0, fmt.Errorf("likely misread: frequency_2 read %v", n)
}
if n == 100 {
// this translates as 1 Hz, which is unlikely
return 0, fmt.Errorf(" %w: frequency_2 is 1.00Hz", errSkippableRead)
}
return float64(n), nil
} }